SRIK is hiring Hardware Design Developer - Verilog immediately.
Total Years Of exp- 3+ years Mandatory
Opportunity- Full Time Contract, 8 hours
Notice Period: Immediate
Mandatory Skills:
Min of 2 years of relevant experience.
Hardware Design and/or Hardware Verification
Experience with one or more on the list below
ASIC
VLSI
FPGA
SOC
Experience with one more on the list below
System Verilog development
Verilog development
Testbench development and/or verification.
About the Role:
We're searching for an exceptional hardware design Developer to play a pivotal role in using the hardware design platform to generate the training data to enhance enterprise LLMs' capabilities. This unique position offers the chance to directly contribute to the sophistication of enterprise LLMs, ensuring they operate with unparalleled efficiency and intelligence.
Your Mission:
Develop, configure, and customize the hardware design platform, utilizing it to generate vital training data for enterprise LLMs.
Liaise with research teams to translate requirements into actionable data insights, directly impacting our LLMs' performance.
Uphold the highest standards in coding, debugging, and documentation, ensuring the hardware design solutions are optimized for LLM training and benchmarking.
Collaborate across teams to identify and prioritize needs, contributing to the LLMs' ability to understand and automate complex processes.
Job Requirements:
BS or MS degree in Electrical, Engineering, or related field.
3-5 years of proven experience in hardware design development.
Expertise in HDLs such as Verilog, System Verilog, VHDL, and System C.
Expertise in scripting, front-end and verification workflows, and integrations within the hardware design environment.
Exceptional problem-solving, communication, and collaborative skills.
Familiarity with Synopsys/Cadence or open source toolchains
Plus, if You Have
Expertise in UVM environments
Expertise in Formal Verification
Expertise in Lint process and refinement
Experience with Computer Architecture and Assembly Coding and Debugging
Experience with Assertion Coding and SVA
Familiarity with ML and AI systems
Key Experiences:
IP Development - Verification and Front End.
Development - EDA Tools ( VLSI Industry) Verilog + System Verilog
Look for Project Description Including:
Type of Modules - Described in projects that he implemented and integrated.
Engaged in IP, USP,HDM.
Can solve problems and not just connect in the system.
Able to describe and develop test plan
Verification workflow - implementation , Checker System, Test Strategy,
Should be able to provide indication, optimization, Verification to Front End Teams.
They should know what is IP and should be able to solve IP problems.
Look for profiles describing projects integrated in systems, engaging IPs, development of IP
Pre-screening - mandatory questions:
What is your experience with HDLs and scripts? Which ones are you familiar with, and for which applications?
Have you made design improvements (area, timing, performance, capability) in an existent IP (e.g., adders, DSPs, processor, etc.)? If so, tell me why and how you had to improve it.
Have you worked on improving a project's verification lead time? What was your approach and what were the results?
How does the compressed instruction set (RV32C) enhance the performance and efficiency of RISC-V systems?
Have you utilized any open-source LLM (Large Language Models) for convenience in your daily workflows? If so, which ones?
On this job, you won't be working building a project but training an LLM.
About the Role:
We're searching for an exceptional hardware design Developer to play a pivotal role in using the hardware design platform to generate the training data to enhance enterprise LLMs' capabilities. This unique position offers the chance to directly contribute to the sophistication of enterprise LLMs, ensuring they operate with unparalleled efficiency and intelligence.
Your Mission:
Develop, configure, and customize the hardware design platform, utilizing it to generate vital training data for enterprise LLMs.
Liaise with research teams to translate requirements into actionable data insights, directly impacting our LLMs' performance.
Uphold the highest standards in coding, debugging, and documentation, ensuring the hardware design solutions are optimized for LLM training and benchmarking.
Collaborate across teams to identify and prioritize needs, contributing to the LLMs' ability to understand and automate complex processes.
Job Requirements:
BS or MS degree in Electrical, Engineering, or related field.
3-5 years of proven experience in hardware design development.
Expertise in HDLs such as Verilog, System Verilog, VHDL, and System C.
Expertise in scripting, front-end and verification workflows, and integrations within the hardware design environment.
Exceptional problem-solving, communication, and collaborative skills.
Familiarity with Synopsys/Cadence or open source toolchains
Plus, if You Have
Expertise in UVM environments
Expertise in Formal Verification
Expertise in Lint process and refinement
Experience with Computer Architecture and Assembly Coding and Debugging
Experience with Assertion Coding and SVA
Familiarity with ML and AI systems
Key Experiences:
IP Development - Verification and Front End.
Development - EDA Tools ( VLSI Industry) Verilog + System VerilogLook for Project Description Including:
Type of Modules - Described in projects that he implemented and integrated.
Engaged in IP, USP,HDM.Can solve problems and not just connect in the system.
Able to describe and develop test plan
Verification workflow - implementation , Checker System, Test Strategy,
Should be able to provide indication, optimization, Verification to Front End Teams.They should know what is IP and should be able to solve IP problems.
Look for profiles describing projects integrated in systems, engaging IPs, development of IP
Pre-screening - mandatory questions:
What is your experience with HDLs and scripts? Which ones are you familiar with, and for which applications?
Have you made design improvements (area, timing, performance, capability) in an existent IP (e.g., adders, DSPs, processor, etc.)? If so, tell me why and how you had to improve it.
Have you worked on improving a project's verification lead time? What was your approach and what were the results?
How does the compressed instruction set (RV32C) enhance the performance and efficiency of RISC-V systems?
Have you utilized any open-source LLM (Large Language Models) for convenience in your daily workflows? If so, which ones?
On this job, you won't be working building a project but training an LLM.
LinkedIn profile is a must, please do not share any resumes without LinkedIn, Send profile in word format to srikconsulting@yahoo.com || +91 7396682593
LinkedIn Profile :
Position : Permanent with SRIK ( We are in to IT Consulting/Services based company in INDIA (Hyderabad ,Pune) & UK (London ) and South Africa(Cape Town)
2
You need to submit 3 months’ pay slips and bank statement & form 16 as well to release offer letter if selected.
We will do Background Verification as well.
If you are fine let me know, then we can schedule your interview.
We are updating our website, so here is the temp link about company info.
Company INFO : https://srikconsulting.com/index.php
About US:
Website : www.srikconsulting.com ( We are updating our website )
Industry : Information Technology & Services Company
Headquarters : Hyderabad, INDIA
Other Office Locations : London, UK & CapeTown,SouthAfrica
Type : Privately Held
Founded : 30 October 2015
ISO 9001:2015 Certified Company
For more Careers : https://srikconsulting08.blogspot.com
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